Custom 16-bit Pipelined Processor
03/2025 – 06/2025 · UC San Diego (Supervisor: John A. Eldon)
- Defined ISA and implemented datapath, ALU, control, and memory interface in SystemVerilog.
- Validated through assembly simulation and FPGA deployment; executed all benchmark programs stably.
Development Steps
- Define architecture and requirements
- Implement modules in SystemVerilog
- Run simulations and debug
- Deploy on FPGA board